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no we dont reboot because the ME want to

Change-Id: I01da133425c7f6c31031082975ebb2c297b10c9b

Change-Id: Id13ad448587264a868bae2d7dbf83c989ef6c12e

to reduce the time before ram stage. There seems to be
a hidden watchdog or real watch. maybe TCO is retriggering the
smm while init or so.

Change-Id: I320675b10938c65a381229a26e896e2ded4a2991

Change-Id: I21cdc80a69b1524d5c74cdb4b901b345818c2f07

Change-Id: Ia3d6fe1d250571420b0303ffc191a6699910e16a

Change-Id: If32b5fef0d65def20d86fcdab8f420d44f012281

Change-Id: I1ec1709a206abcb684d3019afa813dbdaf3d3b3b

Change-Id: I09cfc78719830ee6bc396a3a6abb7139052a0e06

Add ECC support for native raminit on SandyBridge/IvyBridge.

Change-Id: I1206746332c9939a78b67e7b48d3098bdef8a2ed
Signed-off-by: Patrick Rudolph <siro@das-labor.org>

Add support for detection ECC capability and forced ECC mode.
Print the ECC mode in verbose debugging mode.

Change-Id: I5b7599746195cfa996a48320404a8dbe6820483a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>

Change-Id: If52d9e923ebca6f49b6124a01dc4323e96b97114

Change-Id: I9575525764bcd661a90d04d958de556b902386d6

Change-Id: Ia37b14ffc9db00203eb4eb24f61a5cfacda72ba3

Change-Id: I2eae26ae4b9542bd5b7a4e01bed73d3d8ba6b04c

Change-Id: Iaabc124eb870e176cb17e832c4aa0848a779e363

Change-Id: Idf4ac799197790484daa20bdd7bc104a684cb2a0

Change-Id: I05e70ba1dfe5223040417742a18621d18b7431e8

Change-Id: I3d61bd21589d7d8f5e23b28d6c86ffd2a23fde98

Change-Id: Ie784a33f006491425bc94f8d6fbdd82334a109dd

Change-Id: I3c3c9cd5c2030d1b8d12a855a6409a38eec215ff

Change-Id: I8fb95fe7b85b31e9914446ee810698dbec78dc1a

Change-Id: Ia8305c47473390bdd5249afeec064da3d82a65bc

Add Kconfig Option to build SerialICE shell into coreboot stages.
You can select between romstage and ramstage.
The SerialICE shell will be launched instead of coreboot console.
As minimal system initialization is already done in coreboot, it
should work on all boards.

Tested with EHCI Debug on Lenovo T520 and Lenovo X60.

Needs tests:
 * Ramstage

Change-Id: I1fa6eb4f40e0f625c8c8302d1580bcd2664d670b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Antonello Dettori <dev@dettori.io>

Change-Id: Ib14b4258f872bbf7a7d2e4563c54b2ff49e3ca46

Run an regular or extended memtest on native raminit to make sure the DRAM
is usable. As it's very intrusive, the test is only run on cold-boot, but
not on S3 resume.

Change-Id: I31bcf8348c97b9461ee0aa792b3e53c0225d7d48
Signed-off-by: Patrick Rudolph <siro@das-labor.org>

This reverts commit 293229c7.

Change-Id: I1ed8882dc079343d447413f91dbbb436d8233436

Change-Id: Ibdb8b635b22e3ce7cc6c901e6f3cc604173307e9

This reverts commit 5c5eca8d.

It seems to be Channel 0 Slot 1

Change-Id: I678a279f69e28328bd2cdbd7fde88ebdf6671936

Change-Id: Ib0014ae623ec1f79b6c9db48ac3362c67c19c652

Change-Id: I3c0df329e4b5c3857f7021c900407c973943ac17

Change-Id: Ic7075c09941033c4dc893fcc36b6b19b1ee14154

Change-Id: I8072282a3271d0459cecb7979cf01b331341f72e

Change-Id: Ieff8055a6d23602e689c10d34c0f0657830bacdf

Change-Id: I8ceb869939b81f00fb17fe5da2962ed366c7beb1

Change-Id: I1956dc03b2129384a017fa52ac514965c91cb396

Change-Id: I51ca03a3337f1e4075cdd58784a4a99af2a9468a

Change-Id: If6762453f27714edb6b9d9a8acbcd955525f2688

Add GPE configuration table.

Remove GPE3 from the power button ASL and set the EC to GPE3(AGPIO22).

Set the EC and PCIE/WLAN SCI GPIO signals.

Set GPE ASL methods for:
  PCIE/WLAN      8h
  EHCI          18h
  XHCI          1fh
Note EC GPE3 methods are in the EC ASL.

BUG=b:63268311
BRANCH=none
TEST=Test lidswitch powers the device on and off at the login screen.

Change-Id: I27c880ee84b6797d999d4d5951602b654ede948e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22096Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Add printout before EC hibernates during a cr50 update to clarify that
failure is due to EC rather than cr50.  Ran into a situation where DUT
shut down during cr50 update and the EC was the culprit.

BUG=None
BRANCH=None
TEST=None

Change-Id: I54813fec123de69604d1da4dfc65eaeb77d1662e
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22120Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>